In order to increase the memory capacity of a nonvolatile semiconductor memory device (memory), it is necessary to reduce the dimensions of one element. In order to solve difficulties in relation to cost and technology accompanying the miniaturization of elements, a collectively processed three-dimensional stacked memory cell is proposed.
In the collectively processed three-dimensional stacked memory cell, insulating layers and electrode films (functioning as word lines) are alternately stacked to form a stacked body, and through holes are formed collectively in the stacked body. Then, on the side surface of the through hole, a charge storage film (memory layer) is formed, and silicon is embedded inside the through hole to form a silicon pillar. Between the charge storage film and the silicon pillar, a tunnel insulating layer is provided and between the charge storage film and the electrode film, a block insulating layer is provided. In this manner, a memory cell including, for example, a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor is formed at each of the intersection portions of the electrode films and the silicon pillars.
In a NAND flash memory, when data is newly rewritten, a certain region is collectively erased and new data is written. At this time, there is a case where it is preferable to reduce the size (block size) of the region (block) to be collectively erased. On the other hand, if the block size is reduced, one NAND string becomes small and the number of NAND strings increases, which induces an increase in a driver circuit (control unit). In a nonvolatile semiconductor memory device, it is desired to reduce the block size without inducing an increase in the control unit.